Integrated circuit designs have numerous active devices such as transistors laid out on a common substrate, typically silicon. A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of active devices and circuit features.
In order to achieve higher device density, smaller geometry devices have been developed. Isolation regions separate the active devices to prevent electrical interference between them. Such isolation regions may be formed early in the fabrication process by masking the active regions and growing an insulator, such as an oxide, in the non-masked isolation regions. The grown oxide, referred to as a field oxide, serves to isolate and define the active regions. The active devices are formed by various processing steps and then covered with an insulator.
In order to interconnect the various active devices, one or more overlying metalization layers are formed on top of the insulator with connections to the devices provided by conductively filled openings in the insulator. The various devices are thereby interconnected between adjacent active devices that may be disposed underneath the insulating layer. The initial interconnection, known as local interconnects ("LI"), is formed between transistors on the main surface of the semiconductor substrate.
A local interconnect is typically formed between two active devices, e.g., the source/drain region of the transistor and gate electrode of a neighboring transistor. However, local interconnects may also be formed between polysilicon gate regions. In general, local interconnects are used to electrically connect electrodes of active devices within an integrated circuit to provide an electrical connection between two or more conducting or semi-conducting regions (e.g., active regions of one or more devices). For example, a plurality of transistors can be connected to form an inverting logic circuit using a local interconnect.
Local interconnects typically comprise a relatively low-resistance material, such as a conductor or doped semiconductor, that is formed to electrically couple the selected regions. For example, in certain arrangements, damascene techniques are used to provide local interconnects made of tungsten (W), titanium/titanium nitride or a like conductor metal, which is deposited within an etched opening.
Sidewall spacers, also known as lightly-doped drain (LDD) spacers are typically formed on the side surfaces of gate electrodes to electrically isolate the gate electrode from source and drain contacts or interconnects. Sidewall spacers generally prevent heavy-dose source/drain implants from completely overlapping LDD regions next to the gate. In addition, sidewall spacers may be formed to allow the removal of subsequently formed dielectric layers without the possibility of removing a portion of a conductive device around which the sidewall spacer is formed, i.e., they may be used as a mask. Sidewall spacers are typically formed by depositing a conformal layer of dielectric material followed by anisotropic etch back techniques. Conventional dielectric materials employed to form sidewall spacers include SiO.sub.2, SiO.sub.2, or SiN, which have a dielectric constant K of about 4 to about 7.
As circuit density increases, demands for more efficient, effective and precise processes for forming smaller local interconnects increase. However, as devices are scaled into the deep sub-micron range, as with a design rule of about 0.18 microns and under, e.g., about 0.15 micron and under, the increased capacitance between a gate electrode, e.g., doped polysilicon, and a tungsten or copper local interconnect, becomes significant. These narrow spaces are frequently filled with a high dielectric constant material, such as SiN or SiON. As such, it has been found difficult to provide low RC (resistance capacitance) interconnection patterns, particularly where sub-micron via contacts and trenches have high aspect ratios imposed by miniaturization. Accordingly, there is need to reduce the composite dielectric constant of the materials between a gate electrode and local interconnection ("poly-LI"). It would be advantageous if the composite K between gate-LI is lowered to a range of about 3 to about 5.5, preferably 4.2 to about 4.7. Lower-K materials provide less capacitance, increasing the propagation speed of electrical signals. Thus, the use of lower K materials in the formation of sidewall spacers would provide a semiconductor chip with an overall lower RC delay and an improved operating speed relative to prior designs.